1. Field of the Invention
The present invention generally relates to semiconductor chip manufacturing processes and more particularly to dual gate oxide, dual work function field effect transistor manufacturing processes that may be adapted for manufacturing merged logic and dynamic random access memory chips.
2. Background Description
Dynamic random access memory (DRAMs) and logic designs have different design points and requirements. Logic design is focused, typically, on speed at the cost of increased power. Consequently, high device leakage current can be tolerated. By contrast, the primary focus in DRAM design is minimizing leakage currents that would otherwise reduce memory cell data retention time.
State of the art IC chips must be able to allow wider ranges of on-chip voltages, while increasing circuit performance and design flexibility.
For example in DRAM designs, it is necessary to boost the wordline voltage above the circuit power supply voltage to increase the charge stored on storage nodes and to improve resulting signals read therefrom.
However, boosting wordline voltage increases the electric field across the gate dielectric of transfer devices tied to the wordline. Therefore, to satisfy gate dielectric reliability requirements, the transfer gate's dielectric is thickened. For a typical DRAM chip with a uniform gate oxide thickness, the thickened gate oxide degrades performance in peripheral circuits and input/output (I/O) circuits. While this degradation may cause an acceptable impact in DRAM performance, when a DRAM is merged with high performance logic, the logic becomes prohibitively slow. There is, therefore, some reluctance in merging high performance logic with DRAM cells on a single chip, because of the inherent increase in process complexity.
Another problem is transient voltage spikes on I/O device gate oxide from I/O voltage overshoots and undershoots. These voltage spikes require special decoupling to reduce the spikes' magnitude. These decoupling structures occupy additional chip area and add to design complexity. So, techniques have been suggested, known as dual gate processes, to provide two different gate oxide thicknesses on the same chip in order to both improve logic performance and increase circuit design flexibility.
In the simplest such dual gate oxide process, an initial gate oxide is grown. Then, the gate oxide is photolithographically patterned to protect thick gate oxide region and expose thin oxide gate regions. Then, the oxide is etched from the exposed regions. The mask is removed and, oxide is grown in the thin oxide regions and simultaneously thickened in the initially protected gate oxide regions.
A major drawback of this method is that coating the first gate oxide layer with photoresist and then stripping the photoresist may reduce chip yield and degrade reliability. "Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing" by Doyle, B., Saleimani, H. R. and Philiposian A. in IEEE Electron Device Letters Vol. 16, No.7, pp. 301-1 (1995), teach another approach to growing dual gate oxides on a single chip. Doyle et al. teach selectively implanting nitrogen into surface of the substrate in thin gate oxide regions. The presence of nitrogen retards oxide growth in thin oxide regions. Then, when oxide is grown, simultaneously in both regions, oxide grows slower in thin oxide regions. As a result, thick gate oxide grows everywhere except in regions implanted with nitrogen. While the Doyle et al. technique has been shown to be technically feasible, repeatable results are yet to be shown.
Still another problem complicating a merged DRAM/logic process is the need for forming dual work function gate conductors, i.e., P-type in P-type field effect transistors (PFETs) and N-type in N-type field effect transistors (NFETs), without disturbing the polysilicon-tungsten-nitride gate stack in the DRAM cells. This is especially difficult without increasing overall process complexity. It is equally difficult to avoid the reduced DRAM cell retention time and metal contamination arising from selectively forming silicides only on logic circuits as may be desired.
Thus, there is a need for a reliable merged DRAM/logic process with selectively formed dual gate oxide thicknesses.